Stage	iOPl V, rB
Fetch	icode : ifun <- M1[PC] rA : rB <- M1[PC+1] valC <- M4[PC+2] valP <- PC + 6
Decode	valA <- valC valB <- R[rB]
Execute	valE <- valB OP valA Set CC
Memory	
Write back	R[rB] <- valE
PC update	PC <- valP

Stage	leave
Fetch	icode : ifun <- M1[PC] valP <- PC + 1
Decode	valA <- R[%ebp]
Execute	valE <- valA + 4
Memory	valB <- M4[valE]
Write back	R[%esp] <- valE R[%ebp] <- valB
PC update	PC <- valP

2003-11-13T20:46:09